1. Field of the Invention
The present invention relates to an oscillator and a frequency synthesizer and, more particularly, to a voltage controlled digital analog oscillator and a frequency synthesizer using the same.
2. Discussion of Related Art
An integer-N frequency synthesizer according to a prior art will be described with reference to FIGS. 1 to 4.
FIG. 1 is a block diagram of an integer-N frequency synthesizer according to a prior art, which employs a phase locked loop (hereinafter, referred to as PLL) with a negative feedback. As shown in FIG. 1, the conventional frequency synthesizer is composed of primary blocks, as follows: an R divider 110 for outputting a frequency fREF obtained by dividing a reference frequency fXTAL supplied from the exterior by R; a phase frequency detector (PFD) 120 for comparing frequencies and phases of two input signals fREF and fDIV, and outputting signals DN and UP, corresponding to the differences; a current pump (CP) 130 for outputting charges corresponding to the outputs DN and UP of the phase frequency detector to a low pass filter (hereinafter, referred to as LPF); the LPF 140 for serving as a loop filter for the entire frequency synthesizer and for supplying a voltage, which controls an output frequency fVCO of a subsequent voltage controlled oscillator (hereinafter, referred to as VCO); the VCO 150 for outputting an oscillating frequency fVCO in proportion to an input control voltage; and an N divider 160 for performing a dividing operation to implement a frequency ratio N of the output frequency fDIV of the N divider to the output frequency fVCO of the VCO so that a desired VCO output frequency fVCO is obtained. A serial-to-parallel (S-to-P) block 170 is a subsidiary block for supplying serial digital data from the exterior into the frequency synthesizer in parallel.
The conventional frequency synthesizer, as described above, forms a negative feedback loop. Thus, if the dividing ratio of the N divider 160 is determined, the frequency and phase synchronizing process is performed on two input signals of the phase frequency detector 120, and then the frequencies and phases are synchronized, so that a higher frequency fVCO is obtained by the synthesis at the output of the VCO 150, in which the higher frequency is equal to N times the output frequency fREF of the R divider.
The VCO 150 in the frequency synthesizer may be implemented in several manners and types according to a required output frequency or an application field. In a radio frequency (RF) front end, which requires a higher output frequency and a considerably excellent phase noise property, the VCO is implemented by creating negative resistance using an active circuit, namely, using a positive feedback, for compensating an energy loss (generated at parasitic resistance components) in an LC resonant circuit or an LC resonant network, which generally makes use of one inductor and one capacitor. This LC-tuned VCO can vary inductance L or capacitance C of an LC resonator in order to vary an output frequency according to an input control voltage. Generally, the variance of a capacitor is easier to be implemented than the variance of an inductor. Consequently, the LC-tuned VCO primarily includes an inductor having fixed inductance and a varactor having capacitance capable of being varied depending on an input voltage.
FIG. 2 is a circuit diagram of a differential LC tuned VCO that is used in the frequency synthesizer structure according to the prior art illustrated in FIG. 1. In FIG. 2, the VCO is composed of inductors 210 in a resonant circuit; variable capacitors 220 in the resonant circuit; active elements 230 composed of transistors for allowing the LC resonant circuit to continue to maintain resonance by obtaining negative resistance through a formed negative feedback; and an active element 240 for providing a current bias for the resonant circuit.
FIG. 3 illustrates a simplified curve of an output frequency to an input voltage of the VCO that uses the inductor and the variable capacitor represented in FIG. 2. In FIG. 3, it can be seen that the output frequency fvco is proportion to an input voltage V, continuously.
The VCO shown in FIGS. 2 and 3 must satisfy a frequency tuning range needed for any system in a predetermined range of the control voltage. Therefore, as shown in FIG. 3, a VCO gain indicating a ratio of the change in frequency to the change in control voltage is represented by Equation 1.
                              VCO          ⁢                                          ⁢          gain                =                              Δ            ⁢                                                  ⁢                          f              VCO                                            Δ            ⁢                                                  ⁢                          V              control                                                          Equation        ⁢                                  ⁢        1            
As seen from Equation 1, the broader a needed frequency band, the larger a defined VCO gain.
In addition, the frequency change in the VCO results from the capacitance change in the resonant circuit. As a variable capacitor, a P-N junction varactor or an accumulation mode MOS varactor may be used, in which the varactor is based on the junction capacitance varied depending on an applied voltage in a silicon process. The performance index of the variable capacitor may be represented by Equation 2.
                              Tuning          ⁢                                          ⁢          capability                =                              C            max                                C            min                                              Equation        ⁢                                  ⁢        2            
In Equation 2, Cmax means the maximum variable capacitance and Cmin means the minimum variable capacitance.
A capacitor with larger capacitance should be used to expand the range of the variable capacitances in such variable capacitors. However, there is a problem that non-variable parasitic capacitance increases as the variable capacitances increase. Further, in the case of using a varactor with larger capacitance at any desired frequency an inductor with relatively smaller inductance should be used, resulting in the increases of current consumption.
Further, the increase in the variable capacitance leads to the increase of the VCO gain, whereby large noise that incomes over an input signal line controlling the frequency of the VCO becomes generated at the output of the VCO, and thus, the performance of the frequency synthesizer gets deteriorated. Phase output noise of the VCO to the noise incoming over the input signal line, L{ωm}, is represented by Equation 3.
                              L          ⁢                      {                          ω              m                        }                          =                              (                                                            K                  VCO                                ·                                  A                  m                                                            2                ·                                  ω                  m                                                      )                    2                                    Equation        ⁢                                  ⁢        3            
In Equation 3, KVCO indicates the gain of the VCO, Am indicates the size of input noise, and ωm indicates the offset angle frequency. It can be further analogized from this equation that, in FIG. 3, phase noise appearing at a center portion having the largest VCO gain is not good and the phase noise appearing at both edges having no VCO gain is the best. Consequently, there are problems that it is difficult to obtain an excellent phase noise output over a whole frequency variance range of the VCO and also to obtain consistent performance.
FIG. 4 shows a result of a simulation experiment for a frequency synchronizing process in the frequency synthesizer using the VCO having the inductor and the variable capacitor according to the prior art as represented in FIG. 1. When the dividing ratio N is changed, the frequencies and the phases are finally synchronized through a nonlinear frequency synchronizing process, and thus, reaching a locking state, so that a desired synthesized frequency is obtained at the output of the VCO.
The integer-N frequency synthesizer according to the prior art, as described above, has some problems that in a state where both the frequencies and the phases are synchronized, several mismatches are generated between UP and DOWN currents created in the current pump, and spur with large noise power is created at the output of the VCO due to the noise having a period of the input frequency of the phase frequency detector. It is noted that this spur appears in proportion to the VCO gain. Therefore, the spur output can be reduced when the VCO gain is reduced in a constant size of any periodic signal. However, a total loop gain would be reduced if only the VCO gain is reduced in designing the PLL loop. Thus, there is a problem that VCO output phase noise of in-band, and input phase noise of the phase frequency detector, the current pump or the like of out-band may increase due to the reduced loop gain, in case where the PLL is in a locking state.
Hereinafter, a fractional-N frequency synthesizer according to a prior art will be described with reference to FIG. 5.
FIG. 5 is a fractional-N frequency synthesizer according to a prior art. As shown in FIG. 5, the fractional-N frequency synthesizer comprises an N/N+1 divider 180 and an accumulator 190 in place of the N divider of the integer-N frequency synthesizer, as compared the fractional-N frequency synthesizer with the integer-N frequency synthesizer according to the prior art illustrated in FIG. 1. Other blocks are the same in the two frequency synthesizers. The N/N+1 divider 180 is a divider circuit having a dual—modulus dividing ratio of dividing ratios N and N+1, in which one of the N and N+1 dividing ratios is selected by a carry signal. The accumulator 190 accumulates incoming values and generates the carry signal according to the result. With such a configuration, the fractional-N frequency synthesizer can output a frequency between N times and N+1 times the output frequency fREF of the/R divider as a VCO output frequency fVCO. However, the present fractional-N frequency synthesizer also has problems similar to the aforementioned integer-N frequency synthesizer.